Methods of exposing conductive vias of semiconductor devices and related semiconductor devices

ABSTRACT

Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.13/733,508, filed Jan. 3, 2013, the disclosure of which is incorporatedherein in its entirety by this reference.

FIELD

The disclosure relates generally to semiconductor devices andsemiconductor device fabrication. More specifically, disclosedembodiments relate to methods of manufacturing semiconductor devicesthat may improve reliability and quality when exposing conductive vias.

BACKGROUND

To facilitate electrical connection of circuitry on active surfaces ofsemiconductor devices, conductive vias may be formed from an activesurface extending into a substrate comprising a semiconductor material.Ends of the conductive vias may be exposed at an opposing backsidesurface of the substrate. Such vias are commonly referred to as“Through-Silicon Vias” or “Through-Substrate Vias” (TSVs). Eachconductive via may be isolated (electrically and physically) from thesubstrate with a dielectric layer having a thickness of between about 50nm and about 1,000 nm. Such a dielectric layer may also be referred toas a “spacer layer” or a “liner.” After the spacer-layer-encapsulatedpillars of the conductive vias have been revealed by selectivelyremoving material from the backside surface of the substrate, thebackside surface of the substrate may be protected by depositing abarrier layer (e.g., of silicon nitride or silicon carbide) to preventfrom diffusion of other materials (e.g., copper) into the substrate,forming electrical shorts between the conductive vias and the substrate.In addition, an oxide passivation layer may be deposited over thebarrier layer to provide additional protection to the backside surfaceof the substrate and the barrier layer itself, as well as to isolate theconductive vias from one another. Thus, the chances of the metalmaterials contaminating the substrate, shorts forming between theconductive vias, and shorts forming between the conductive vias and thesubstrate may be significantly reduced. FIGS. 1A through 1E depict aconventional process for exposing the conductive material of a TSV inpreparation for electrical connection.

With reference to FIG. 1A, a semiconductor device 100 in an intermediatestate of fabrication is shown. The semiconductor device 100 comprises athinned substrate 102 of semiconductor material such as, for example, asemiconductor wafer after backside grinding. The thinned substrate 102is attached to a carrier substrate 104 using a temporary adhesive 106for structural support during processing and handling. The grindingprocess may be relatively rapid, though imprecise, which may leavesignificant thickness variation in the remaining material of thesubstrate 102. Consequently, the ends of some conductive vias 108 may bemuch farther from a backside surface 112 of the substrate 102 than endsof other conductive vias 108. A conductive via 108 encapsulated in aspacer oxide shell 109 extends from an active surface 110 of thesubstrate 102 toward an opposing backside surface 112 of the substrate102. As shown in FIG. 1B, a portion of the semiconductor material of thesubstrate 102 may be removed from the backside surface 112 by, forexample, a dry etch process to expose the conductive via 108 at thebackside surface 112. The material removal process may be selective,such that the spacer oxide shell 109 remains intact, reducing the riskof metal contamination to the exposed substrate 102. Referring to FIG.1C, a barrier material 114, which may comprise silicon nitride (e.g.,Si₃N₄), may be deposited over the backside surface 112 and the exposedportion of the conductive via 108, including the associated spacer oxideshell 109, using a conformal deposition process, such as, for example, achemical vapor deposition (CVD) or physical vapor deposition (PVD)process. “Conformal deposition processes,” as used herein, include alldeposition processes that are capable of depositing materials to allexposed surfaces of a structure, regardless of orientation, such thatthe topography of the resulting structure generally resembles thetopography the surfaces exhibited prior to deposition. As shown in FIG.1D, an isolation material 116, which may comprise silicon oxide (e.g.,SiO₂ or SiO), may be deposited over the barrier material 114 on a sideopposing the substrate 102 using, for example, a conformal depositionprocess.

Referring to FIG. 1E, a portion of the isolation material 116, thebarrier material 114, the spacer oxide shell 109, and the conductive via108 may be removed to render a bottom surface 118 of the semiconductordevice 100 substantially planar and expose an end of the conductive via108 for electrical connection. For example, an abrasive planarizationprocess, such as chemical-mechanical planarization (CMP) process, may beemployed. The CMP process may stop before all of the isolation material116 has been removed. The resulting semiconductor device 100 may includethe barrier material 114 extending laterally over the backside surface112 of the substrate 102 and longitudinally around a periphery of theconductive via 108. The isolation material 116 may extend laterally overthe barrier material 114 and terminate at a portion of the barriermaterial 114 that extends longitudinally to cover a lateral exteriorsurface of the spacer oxide shell 109 surrounding the conductive via108.

Conductive vias 108 exposed using the process described in connectionwith FIGS. 1A through 1E require deposition of a relatively thick layerof isolation material 116 (see FIG. 1D) to ensure all the conductivevias 108 are covered because the protruding height of individual vias108 may vary significantly across an entire wafer. In addition, there isno clear indicator for when removal of the isolation material 116 andthe barrier material 114 (see FIG. 1E) should stop. Insufficient removalmeans that some conductive vias 108 may not be exposed properly. Toomuch removal, especially by a mechanical process, such as CMP, may causethe conductive vias 102 to bend or otherwise deform, or even collapsedue to applied shear force, compromising the connectivity of thesemiconductor device 100, or may expose the substrate 102 tocontamination by consuming all of the barrier material 114.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through 1E are cross-sectional views of a semiconductor deviceundergoing a conventional process for exposing a conductive via of thesemiconductor device.

FIG. 2 is a flowchart of acts in a process according to embodiments ofthe disclosure for exposing conductive vias of a semiconductor device.

FIGS. 3A through 3G are cross-sectional views of a semiconductor deviceundergoing a process for exposing conductive vias of the semiconductordevice according to an embodiment of the disclosure.

FIGS. 4A through 4D are cross-sectional views of a semiconductor deviceundergoing another process for exposing conductive vias of thesemiconductor device according to another embodiment of the disclosure.

FIGS. 5A through 5D are cross-sectional views of a semiconductor deviceundergoing yet another process for exposing conductive vias of thesemiconductor device according to another embodiment of the disclosure.

FIG. 6 is a block diagram of an electronic system comprising asemiconductor device, such as, for example, any of those shown in FIGS.3F, 3G, 4D, and 5D.

DETAILED DESCRIPTION

The illustrations presented herein are not meant to be actual views ofany particular act in a method of fabricating a semiconductor device,intermediate product of such a method, semiconductor device itself, orcomponent thereof, but are merely idealized representations employed todescribe illustrative embodiments. Thus, the drawings are notnecessarily to scale. Additionally, elements common between figures mayretain the same or similar numerical designation.

Disclosed embodiments relate generally to methods of manufacturingsemiconductor devices that may improve reliability and quality whenexposing conductive vias. More specifically, disclosed are embodimentsof methods of exposing conductive vias at a backside surface of asemiconductor device that may ensure all conductive vias of asemiconductor device are exposed for connection, reduce (e.g., prevent)the occurrence of damage to the conductive vias and the substrate,increase control over the process by which the conductive vias areexposed, and decrease the likelihood that the substrate may be exposedto contamination.

Referring to FIG. 2, a flowchart of acts in embodiments of a method 200for exposing conductive vias of a semiconductor device is shown. Abarrier material comprising a nitride may be formed (e.g., deposited)over revealed portions of conductive vias, which may be covered by aspacer material (e.g., an oxide), extending from a backside surface of asubstrate, as indicated at 202. The barrier material may be formed usinga conformal deposition process, such as, for example, a CVD or PVDprocess, such that the barrier material conforms to a topography of asubstrate surface, including protruding conductive vias and anyassociated spacer material. In other words, the topography of theexposed surfaces on a surface (e.g., a backside surface) of thesubstrate opposing the active surface after deposition of the barriermaterial may resemble the topography of the exposed surfaces prior tosuch deposition, although some variation in topography is to be expecteddue to the added barrier material. The barrier material may comprise,for example, silicon nitride (e.g., Si₃N₄) or silicon carbide (e.g.,SiC). A thickness of the barrier material may be less than a protrudingheight of the shortest conductive via, as measured from the backsidesurface of the substrate from which the vias protrude.

A self-planarizing isolation material may be formed over the barriermaterial, as indicated at 204. The topography of the exposed surfaces onthe backside of the substrate after formation of the self-planarizingisolation material may differ significantly from the topography of theexposed surfaces prior to such formation. For example, the topographyafter formation of the self-planarizing isolation material may besubstantially planar (e.g., may exhibit some curvature and surfaceirregularities due to surface tension and wetting to the conductive vias212), whereas the topography before deposition may exhibit peaks andvalleys defined by the substrate, the protruding conductive vias, andthe conformal barrier material. As another example, the topography afterdeposition of the self-planarizing isolation material may besubstantially planar with intermittent interruption by small portions oflonger conductive vias and their associated overlaid barrier material.The self-planarizing isolation material may be non-conformal. In otherwords, an exposed surface of the self-planarizing isolation material mayrender itself at least substantially planar, such as, for example, as aprecursor material of the self-planarizing isolation material flowsunder the influence of gravity and, in the case of a so-called “spin-on”dielectric material, centrifugal force applied by rotation of thesubstrate as a flowable precursor dielectric material is dispensed ontothe substrate surface. The precursor material of the self-planarizingisolation material may be cured (e.g., hardened) to complete theself-planarizing isolation material, which may provide structuralsupport to and isolate the conductive vias and their associated barriermaterial and spacer material. Curing conditions may be selecteddepending on the material selected for use as the self-planarizingisolation material and, therefore, are not described in detail herein.

A portion of the self-planarizing isolation material, a portion of thebarrier material, and a portion of protruding material of the conductivevias, including any associated spacer material, may be removed to exposethe conductive vias, as indicated at 206. Material removal may beaccomplished by, for example, a selective etch process,chemical-mechanical polishing (CMP), or a combination of selectiveetching and CMP (e.g., sequentially or contemporaneously).

Material removal may be stopped after exposing a laterally extendingportion of the barrier material, as indicated at 208. Exposure of thelaterally extending portion of the barrier material may generate adetectable difference (e.g., an indication or a signal) in processresponse resulting from a transition in material removed duringprocessing (e.g., from isolation material to barrier material),detection of such a difference or differences enabling the materialremoval process to be stopped after all the conductive vias have beenexposed but before damaging the conductive vias, the substrate, or both.For example, exposure of the laterally extending portion of the barriermaterial may change (e.g., increase or decrease) the torque required tocontinue removing material using CMP because the barrier material may bemore or less abrasion resistant than the self-planarizing isolationmaterial (e.g., may change the coefficient of friction of at the contactinterface between material removal machinery and the material removed).As another example, exposure of the laterally extending portion of thebarrier material may enable detection of an increase in removal ofbyproducts, such as of ammonia (NH₃) in the waste liquid of a CMPprocess due to the hydrolysis of nitride material in aqueous solution,which may be detected by a liquid or gas sensor. As yet another example,exposure of the laterally extending portion of the barrier material maychange (e.g., increase or decrease) the reflectivity of the exposedsurface, which may be detected by an optical sensor. Accordingly,forming the barrier material to a thickness less than a protrudingheight of the shortest conductive via and stopping material removalafter exposing a laterally extending portion of the barrier material mayrender the conductive via exposure process more controllable. In methodsencompassed by the disclosure, no conductive vias may remain buriedbelow the barrier material and a clear signal is detected to indicatewhen to stop removing excess material from the substrate surface.Additional details regarding methods for exposing conductive vias andresulting semiconductor devices are disclosed in conjunction with thefollowing drawing figures.

With reference to FIGS. 3A through 3G, cross-sectional views of asemiconductor device 210 undergoing a process for exposing conductivevias 212 of the semiconductor device 210 are shown. Referringspecifically to FIG. 3A, the semiconductor device 210 is shownimmediately after a backside surface 218 of a substrate 216 has beenthinned (e.g., by grinding, etching, or both). Semiconductor material ofthe substrate 216 covers the conductive vias 212, which are formed toprovide connectivity from integrated circuitry (not shown) on activesurface 214 to opposing backside surface 218 of substrate 216. Thesemiconductor device 210 may comprise, for example, memory (e.g., NANDor NOR memory), logic, a processor, an imager, a device encompassingsome combination of these (e.g., as a system on a chip), or any othertype of semiconductor device. The conductive vias 212 may be formed byconventional techniques, which are not described in detail herein. Theconductive vias 212 as formed may extend initially from an activesurface 214 of a substrate 216 comprising semiconductor material towardan opposing backside surface 218 of the substrate 216. The conductivevias 212 may comprise an electrically conductive material, such as, forexample, copper or aluminum. The conductive vias 212 may be encapsulatedin a spacer material 213 (e.g., an oxide shell), to isolate metalmaterial of the conductive vias 212 from semiconductor material of thesubstrate 216. The substrate 216 may be attached to a carrier substrate220 for additional structural support during processing and handlingusing, for example, a temporary adhesive 222 over the active surface214.

Because of processing variations inherent to formation of the conductivevias 212, the conductive vias 212 may not be of uniform length within agiven substrate 216, across a wafer (not shown) including manysubstrates 216, or both. For example, a length L₁ of a longestconductive via 212A may be up to about 1 μm or more greater than alength L₂ of a shortest conductive via 212B. In addition, processingvariations inherent to material removal from the backside surface 218 ofthe substrate 216 (e.g., by grinding) to thin substrate 216 from aninitial thickness of, for example, about 600 μm to about 700 μm to afinal thickness of 150 μm or less may result in the substrate 216 havinga non-uniform thickness T_(S). For example, a total thickness variation(TTV) for the substrate 216 may be between about 6.0 μm and about 7.0 μm(e.g., about 6.5 μm), with a thinner portion of substrate 216 located ina central region and a thicker portion of substrate 216 located aroundan edge thereof.

As shown in FIG. 3B, a portion of the substrate 216 at the backsidesurface 218 may be removed to expose portions of the conductive vias212. For example, the substrate 216 may be subjected to an etchingprocess to remove the semiconductor material of the substrate 216selective to spacer material 213 of the conductive vias 212 so theconductive vias 212, and associated spacer material 213, may remainintact. For example, the lengths (e.g., L₁ and L₂ (see FIG. 3A)) of theconductive vias 212 may not be affected significantly by the materialremoval process used to remove the portion of the substrate 216 toexpose the portions of the conductive vias 212, and any associatedspacer material 213. The TTV for the substrate 216 after removingmaterial from the backside surface 218 of the substrate 216 maydecrease, but may still be significant. For example, the TTV for thesubstrate 216 after removing material from the backside surface 218 maybe between about 5.0 μm and about 6.0 μm (e.g., about 5.5 μm). Althoughthe TTV for the substrate 216 as a whole may decrease, relativedifferences between the level at which the backside surface 218 islocated and terminal ends of the conductive vias 212 may shift uponexposure to the etching process. Consequently, taller conductive vias212 previously located adjacent high (e.g., thick) portions of thesubstrate 216 may now be located adjacent low (e.g., thin) portions ofthe substrate 216, short conductive vias 212 previously located adjacentlow portions of the substrate 216 may now be located adjacent relativelyhigh portions of the substrate 216. Other variation in height differencebetween the backside surface 218 of the substrate 216 and the protrudingportions of the conductive vias 212 before and after etching may alsoresult.

After removal of the semiconductor material from the backside surface218 of the substrate 216, all the conductive vias 212, including anyassociated spacer material 213, may protrude from the backside surface218 of the substrate 216. As a result of variances in formation lengthof the conductive vias 212 and thickness T_(S) of the substrate 216,heights to which the conductive vias 212 protrude from the backsidesurface 218 of the substrate 216 may vary significantly. For example, adifference in height between a tallest protruding portion of aconductive via 212A and a shortest protruding portion of a conductivevia 212B may be between about 3.5 μm and about 5.5 μm. Morespecifically, the difference in height between the tallest protrudingportion of a conductive via 212A and the shortest protruding portion ofa conductive via 212B may be between about 4.5 μm and about 5.0 μm. As aspecific, non-limiting example, a protruding height H₁ of a tallestprotruding portion of a conductive via 212A may be about 8.1 μm and aprotruding height H₂ of a shortest protruding portion of a conductivevia 212B may be about 3.2 μm, resulting in a maximum difference inprotruding height between tallest conductive via 212A and shortestconductive via 212B of about 4.9 μm.

As shown in FIG. 3C, a barrier material 224 may be formed (e.g.,deposited) over the conductive vias 212 and the backside surface 218 ofthe substrate 216 using a conformal deposition process after thesubstrate 216 has been thinned. For example, the barrier material 224may be deposited using a low-temperature CVD or PVD process. Morespecifically, the barrier material 224 may be deposited usingplasma-enhanced chemical vapor deposition (PECVD) at between roomtemperature (e.g., about 25° C.) and about 250° C. As specific,non-limiting examples, PECVD may be performed at between about 150° C.and about 200° C. using SiH₄, NH₃, and N₂ gases to form tetraethylorthosilicate (TEOS) and deposit the barrier material 224, using SiH₄and N₂O gases to deposit the barrier material 224, or using TEOS and O₂gases to deposit the barrier material 224 over the conductive vias 212,including any associated spacer material 213, and backside surface 218.As another example, the barrier material 224 may be formed fromsemiconductor material of a portion of the substrate 216 at the backsidesurface 218 using a diffusion process. As yet another example, thebarrier material 224 may be formed from hydrogenated nanocrystallinesilicon carbide using low-temperature (e.g., as low as about 150° C.)helicon wave plasma-enhanced CVD. The resulting barrier material 224 maycomprise, for example, a nitride, an oxide, a carbide, or anycombination of these. More specifically, the barrier material 224 maycomprise, for example, silicon nitride (e.g., Si₃N₄), silicon oxide(e.g., SiO₂), silicon carbide (e.g., SiC), or some combination of thesematerials (e.g., Si₃N₄ and SiO₂ or an SiON material). Because thebarrier material 224 conforms to the conductive vias 212 and thebackside surface 218, the topography of an exposed surface of barriermaterial 224 after its deposition may generally resemble the topographyof the conductive vias 212, including any associated spacer material213, and the backside surface 218 prior to depositing the barriermaterial 224.

A thickness T_(BM) of the barrier material 224 may be less than theprotruding height H₂ of the shortest protruding portion of a conductivevia 212B. More specifically, the thickness T_(BM) of the barriermaterial 224 may be less than a difference between the protruding heightH₂ of the shortest protruding portion of a conductive via 212B and anelevation of a thickest portion of the substrate 216. For example, thethickness T_(BM) of the barrier material 224 may be less than about 1.5μm. The thickness T_(BM) of the barrier material 224 may be sufficientlygreat that the risk of damaging the conductive vias 212, and thesubstrate 216, through bending or toppling may be significantly reduced(e.g., prevented). For example, the thickness T_(BM) of the barriermaterial 224 may be greater than about 800 Å. As a specific,non-limiting example, the thickness T_(BM) of the barrier material 224may be between about 800 Å and about 2,500 Å.

Referring to FIG. 3D, a self-planarizing isolation material 226 may beformed over the barrier material 224. The self-planarizing isolationmaterial 226 may not conform to the topography of the barrier material224, rendering the resulting topography of an exposed surface ofisolation material 226 significantly different from the topography ofthe barrier material 224 prior to deposition of the self-planarizingisolation material 226. For example, the self-planarizing isolationmaterial 226 may be flowable. More specifically, the self-planarizingisolation material 226 may exhibit, for example, a sufficiently lowviscosity to flow around the protruding portions of the conductive vias212 and over the backside surface 218 of the substrate 216 under theinfluence of gravity and in some cases, centrifugal force, rendering anexposed surface of the self-planarizing isolation material 226 planar.The self-planarizing isolation material 226 may be formed over thebarrier material 224 using a deposition process conventionally used forflowable materials, such as, for example, spin-coating or nozzledispensing, which may be followed by a curing process to harden theself-planarizing isolation material 226. The self-planarizing isolationmaterial 226 may comprise, for example, any conventional resist material(e.g., poly(methyl methacrylate) (PMMA), poly(methyl glutarimide)(PMGI), phenol formaldehyde resin, etc.), a spin-on dielectric such as apolyimide, a polynorbornene, benzocyclobutene (BCB),polytetrafluoroethylene (PTFE), an inorganic polymer such as hydrogensilsesquioxane (HSQ) or methylsilsesquioxane (MSQ), or a spin-on glass(SOG) such as a siloxane-based organic SOG or a silicate-based inorganicSOG.

A thickness T_(SPIM) of the self-planarizing isolation material 226 maybe sufficiently great to structurally support the protruding portions ofthe conductive vias 212 during subsequent material removal processes.For example, the thickness T_(SPIM) of the self-planarizing isolationmaterial 226 may be greater than the protruding height H₁ of the tallestprotruding portion of a conductive via 212A. More specifically, thethickness T_(SPIM) of the self-planarizing isolation material 226 maybe, for example, greater than about 2 μm, greater than about 5 μm, oreven greater than about 10 μm. The self-planarizing isolation material226 may be selected to exhibit a removal rate that is significantlyfaster than a removal rate of the barrier material 224. For example, theself-planarizing isolation material 226 may be chemically more reactiveor mechanically weaker (e.g., softer and less abrasion resistant) thanthe barrier material 224 in response to a CMP process. In addition, theself-planarizing isolation material 226 may be removable using aselective material removal process (e.g., a selective dry etch, whichmay also be characterized as a reactive ion etch (RIE)), which may notremove significant quantities of the barrier material 224, in someembodiments.

In some embodiments, a portion of the self-planarizing isolationmaterial 226 may be removed, as shown in FIG. 3E, to reduce thethickness T_(SPIM)′ of the self-planarizing isolation material 226. Thepartial removal may be done using relatively fast material removalmethods (e.g., non-selective dry etch or aggressive CMP) to reduceprocessing time. More specifically, a portion of the self-planarizingisolation material 226 may be removed at a rate faster than a rate ofremoval for a conformal isolation material 116 (see FIG. 1E) comprisingsilicon oxide using CMP. For example, a selective material removalprocess (e.g., a selective dry etch) may be used to remove the portionof the self-planarizing isolation material 226, leaving the barriermaterial 224 and the conductive vias 212, including any associatedspacer material 213 intact. After selectively removing the portion ofthe self-planarizing isolation material 226, portions of the conductivevias 212, particularly the tallest conductive vias 212, and associatedbarrier material 224 may protrude from the self-planarizing isolationmaterial 226. As another example, a non-selective material removalprocess (e.g., CMP) may be used to remove some of the self-planarizingisolation material 226, portions of the conductive vias 212,particularly the tallest conductive vias 212, and associated portions ofthe barrier material 224. Partial removal may leave sufficientquantities of the self-planarizing isolation material 226 between theconductive vias 212 to provide additional structural support duringsubsequent material removal processes, reducing (e.g., preventing) theoccurrence of toppling.

As shown in FIG. 3F, a portion of the self-planarizing isolationmaterial 226, a portion of the barrier material 224, and a portion ofthe protruding sections of the conductive vias 212, including a portionof any associated spacer material 213, may be removed to expose theconductive vias 212 for electrical connection. The removal process maycomprise, for example, CMP. Removal of the materials may take place at aslower rate than a material removal performed earlier in the process ofexposing the conductive vias 212 (see FIG. 3E), enabling greater controlfor stopping the removal process after all conductive vias have beenexposed, but before damaging the conductive vias 212, including anyassociated spacer material 213, and the substrate 216.

The removal process may be stopped when one or more laterally extendingportions of the barrier material 224 are exposed. When referring to“laterally extending portions” of the barrier material 224, what ismeant are the portions of the barrier material 224 extendingsubstantially horizontally over (e.g., directly abutting) the backsidesurface 218 of the substrate 216 between the conductive vias 212, asopposed to the substantially vertically extending portions conforming toperipheries of the conductive vias 212 and the substantiallyhorizontally extending portions formed over the conductive vias 212. Inother words, at least one portion of the self-planarizing isolationmaterial 226 located between conductive vias 212 may be completelyremoved, which portion may be located, for example, over a thickestportion of the substrate 216. Because the thickness T_(BM) (see FIG. 3C)of the barrier material 224 is less than a difference between theelevation of the thickest portion of the substrate 216 and theprotruding height H₂ (see FIG. 3E) of the shortest conductive via 212B,stopping removal after encountering a laterally extending portion of thebarrier material 224 may ensure that all conductive vias 212 are exposedfor electrical connection.

The exposure of the barrier material 224 may provide a detectabledifference (e.g., a signal or an indication) for when to stop thematerial removal process. For example, the barrier material 224 may besignificantly different from the self-planarizing isolation material 226in one or more material properties, such as, for example, coefficient offriction. Accordingly, complete removal of one or more sections of theself-planarizing isolation material 226 between conductive vias 212 toexpose the barrier material 224 may generate a difference in (e.g.,more) friction between the barrier material 224 and a polishing pad on arotating table of a CMP apparatus (not shown), causing a detectabledifference in reactive torque experienced by the polishing table. Whenthe reactive torque exceeds a predetermined threshold, the materialremoval process may be stopped. As another example, the barrier material224 may contain a significantly higher concentration of nitrogen (e.g.,in the form of nitrides) than is contained by the self-planarizingisolation material 226. Therefore, abrasive-containing liquid (e.g.,slurry) conventionally used during CMP on the polishing pad may contactthe partially or fully exposed barrier material 224 after one or moresections of the self-planarizing isolation material 226 have beenremoved. Nitrides (e.g., silicon nitride) may chemically react withliquid (e.g., acid) of the abrasive-containing liquid, generating agreater quantity of nitrogen-containing species distributed in theliquid phase and causing a detectable difference in the presence of suchspecies (e.g., NH₃H₂O or NH₄ ⁺) in liquid waste. When the presence ofnitrogen in the surrounding environment exceeds a preselected threshold,the material removal process may be stopped. As yet another example, thebarrier material 224 may exhibit a different (e.g., greater or lesser)reflectivity than the self-planarizing isolation material 226.Accordingly, complete removal of one or more sections of theself-planarizing isolation material 226 may change the overallreflective properties of a bottom surface 228 (see FIGS. 3F and 3G) ofthe semiconductor device 210 responsive to exposure of portions ofbarrier material 224, exposure of ends of conductive vias 212, and anyremaining exposed portions of self-planarizing isolation material 226.When the reflectivity of the bottom surface 228 exceeds or falls below apredetermined threshold, the material removal process may be stopped.

In some embodiments, the material removal process used to expose all theconductive vias 212 may be stopped when one or relatively few laterallyextending portions of the barrier material 224 have been exposed,leaving substantial quantities of the self-planarizing isolationmaterial 226 between the conductive vias 212. In such embodiments, thebottom surface 228 may be characterized by exposed connecting surfacesof conductive vias 212 conformally surrounded by barrier material 224,with self-planarizing isolation material 226 remaining between amajority (e.g., a vast majority) of the conductive vias 212 and theirassociated barrier material 224. One or some of the areas adjacent theconductive vias 212, however, will comprise or consist of exposed,laterally extending portions of the barrier material 224, as shown inFIG. 3F. In other embodiments, such as that shown in FIG. 3G, thematerial removal process used to expose all the conductive vias 212 maybe stopped when a majority or all of the laterally extending portions ofthe barrier material 224 have been exposed, leaving insignificantquantities of the self-planarizing isolation material 226 between theconductive vias 212. In such embodiments, the bottom surface 228 may becharacterized by exposed connecting surfaces of conductive vias 212conformally surrounded by barrier material 224, with self-planarizingisolation material 226 being disposed between a minority (e.g., a smallminority or none) of the conductive vias 212 and their associatedbarrier material 224, with none of the self-planarizing isolationmaterial 226 remaining. Most or all of the areas between the conductivevias 212 will comprise or consist of exposed, laterally extendingportions of the barrier material 224. In still other embodiments, thematerial removal process may be stopped at an intermediate stage, withsome significant quantities of self-planarizing isolation material 226remaining and other significant quantities of self-planarizing isolationmaterial 226 being removed. In any event, the presence of a detectablechange indicating when to stop the material removal process may ensurethat all the conductive vias 212 are exposed for connection andsignificantly reduce the risk of damaging the conductive vias 212, thesubstrate 216, or both (e.g., by reducing the risk of forming a shortbetween the conductive vias 212 and the substrate 216).

Accordingly, disclosed herein is a method of exposing conductive vias ofa semiconductor device comprising conformally forming a barrier materialover conductive vias extending from a backside surface of a substrate. Aself-planarizing isolation material may be formed over the barriermaterial. An exposed surface of the self-planarizing isolation materialmay be substantially planar. A portion of the self-planarizing isolationmaterial, a portion of the barrier material, and a portion of protrudingmaterial of the conductive vias may be removed to expose the conductivevias. Removal of the self-planarizing isolation material, the barriermaterial, and the conductive vias may be stopped after exposing at leastone laterally extending portion of the barrier material.

In some embodiments, the method of exposing conductive vias of thesemiconductor device may comprise removing a portion of a substrate at abackside surface opposing an active surface of the substrate to exposeportions of conductive vias. A barrier material comprising siliconnitride, silicon oxide, silicon carbide, or any combination of these maybe conformally formed over the conductive vias to a thickness less thana protruding height of a shortest conductive via. A self-planarizingisolation material may be formed over the barrier material. An exposedsurface of the self-planarizing isolation material may be substantiallyplanar. A portion of the self-planarizing isolation material, a portionof the barrier material, and a portion of protruding material of theconductive vias may be removed to expose the conductive vias. Removal ofthe self-planarizing isolation material, the barrier material, and theconductive vias may be stopped after exposing at least one laterallyextending portion of the barrier material abutting the backside surfaceof the substrate.

Also disclosed herein is a semiconductor device comprising conductivevias in a substrate and comprising exposed surfaces at a backsidesurface of the substrate. A barrier material comprising silicon nitride,silicon oxide, silicon carbide, or any combination of these may surroundthe conductive vias. A self-planarizing isolation material may belocated over at least a portion of the barrier material and between theconductive vias. At least one laterally extending portion of the barriermaterial may be exposed adjacent an associated conductive via.

Referring to FIGS. 4A through 4D, cross-sectional views of asemiconductor device 210′ undergoing another process for exposingconductive vias 212 of the semiconductor device 210′ are shown. Afterthe barrier material 224 has been conformally formed over the conductivevias 212 and the backside surface 218 of the substrate 216 (see FIG.3C), a conformal isolation material 230 may be formed over the barriermaterial 224, as shown in FIG. 4A. The conformal isolation material 230may substantially conform to the shape of the barrier material 224 sothat the resulting topography after depositing the conformal isolationmaterial 230 generally resembles the topography of the barrier material224. The conformal isolation material 230 may comprise, for example, anoxide, a nitride, a carbide, or any combination of these. Morespecifically, the conformal isolation material 230 may comprise siliconoxide (e.g., SiO₂), silicon nitride (e.g., Si₃N₄), silicon carbide(e.g., SiC), or any combination of such materials. The conformalisolation material 230 may be deposited over the barrier material 224using a low temperature (e.g., between about room temperature and 250°C.) conformal deposition process, such as, for example, CVD or PVD. Morespecifically, the barrier material 224 may be deposited usingplasma-enhanced chemical vapor deposition (PECVD) at low temperatures.As specific, non-limiting examples, PECVD may be performed at betweenabout 150° C. and about 200° C. using SiH₄, NH₃, and N₂ gases to formtetraethyl orthosilicate (TEOS) and deposit the barrier material 224,using SiH₄ and N₂O gases to deposit the barrier material 224, or usingTEOS and O₂ gases to deposit the conformal isolation material 230 overthe barrier material 224.

A combined thickness T_(C) of the barrier material 224 and the conformalisolation material 230 may be less than the protruding height H₂ of theshortest protruding portion of a conductive via 212B in someembodiments. More specifically, the combined thickness T_(C) of thebarrier material 224 and the conformal isolation material 230 may beless than a difference in elevation between a thickest portion of thesubstrate 216 and the protruding height H₂ of the shortest protrudingportion of a conductive via 212B. For example, the combined thicknessT_(C) of the barrier material 224 and the conformal isolation material230 may be between about 5,000 Å and about 15,000 Å. In someembodiments, the barrier material 224 may comprise between about 800 Åand about 2,500 Å of the combined thickness T_(C), with the conformalisolation material 230 comprising a remainder of the combined thicknessT_(C). In other embodiments, the thickness T_(BM) (see FIG. 3C) of thebarrier material 224 may be less than the difference in elevationbetween the thickest portion of the substrate 216 and the protrudingheight H₂ of the shortest protruding portion of a conductive via 212B,while the combined thickness T_(C) of the barrier material 224 and theconformal isolation material 230 may be greater than that difference inelevation.

Referring to FIG. 4B, a self-planarizing isolation material 226 may beformed over the conformal isolation material 230. The self-planarizingisolation material 226 may not conform to the topography of theconformal isolation material 230, rendering the resulting topographysignificantly different from the topography of the conformal isolationmaterial 230 prior to deposition of the self-planarizing isolationmaterial 226. For example, the self-planarizing isolation material 226may be a non-conformal, flowable material. More specifically, aprecursor of the self-planarizing isolation material 226 may exhibit,for example, a sufficiently low viscosity to flow around the protrudingportions of the conductive vias 212 and over the backside surface 218 ofthe substrate 216 under the influence of gravity and centrifugal force,in some cases (e.g., spin-on application). The self-planarizingisolation material 226 may be formed over the conformal isolationmaterial 230 using a deposition process conventionally used for flowablematerials, such as, for example, spin coating or nozzle dispensing,which may be followed by a curing process to harden the self-planarizingisolation material 226. The self-planarizing isolation material 226 maycomprise, for example, any conventional resist material or spin-ondielectric.

A thickness T_(SPIM) of the self-planarizing isolation material 226 maybe sufficiently great to structurally support the protruding portions ofthe conductive vias 212 during subsequent exposure processes. Forexample, the thickness T_(SPIM) of the self-planarizing isolationmaterial 226 may be greater than the protruding height H₁ of the tallestprotruding portion of a conductive via 212A. More specifically, thethickness T_(SPIM) of the self-planarizing isolation material 226 maybe, for example, greater than about 2 μm, greater than about 5 μm, oreven greater than about 10 μm. The self-planarizing isolation material226 may be selected to exhibit a removal rate that is significantlyfaster than a removal rate of the barrier material 224 and the conformalisolation material 230. For example, the self-planarizing isolationmaterial 226 may be significantly different from the barrier material224 and the conformal isolation material 230 in terms of one or morematerial properties (e.g., abrasion-resistance or reflectivity) orchemical behaviors. In addition, the self-planarizing isolation material226 may be removable using a selective material removal process (e.g., aselective dry etch), which may not remove significant portions of thebarrier material 224 or the conformal isolation material 230, in someembodiments.

In some embodiments, a portion of the self-planarizing isolationmaterial 226 may be removed, as shown in FIG. 4C, to reduce thethickness T_(SPIM)′ of the self-planarizing isolation material 226. Thepartial removal may be done using relatively fast material removalmethods (e.g., selective dry etch or aggressive CMP) to reduceprocessing time. More specifically, a portion of the self-planarizingisolation material 226 may be removed at a rate faster than a rate ofremoval for a conformal isolation material 116 (see FIG. 1E) comprisingsilicon oxide using CMP. For example, a selective material removalprocess (e.g., a selective dry etch) may be used to remove some of theself-planarizing isolation material 226, leaving the conformal isolationmaterial 230, the barrier material 224, and the conductive vias 212,including any associated spacer material 213, intact. After selectivelyremoving a portion of the self-planarizing isolation material 226,portions of the conductive vias 212, particularly the tallest conductivevias 212, and associated conformal isolation material 230 and barriermaterial 224 may protrude from the self-planarizing isolation material226. As another example, a non-selective material removal process (e.g.,CMP) may be used to remove some of the self-planarizing isolationmaterial 226, portions of the conductive vias 212, particularly thetallest conductive vias 212, and associated portions of the conformalisolation material 230 and the barrier material 224. Partial removal mayleave sufficient quantities of the self-planarizing isolation material226 between the conductive vias to provide additional structural supportduring subsequent material removal processes, reducing (e.g.,preventing) the occurrence of toppling.

As shown in FIG. 4D, a portion of the self-planarizing isolationmaterial 226, a portion of the conformal isolation material 230, aportion of the barrier material 224, and a portion of the protrudingsections of the conductive vias 212, and any associated spacer material213, may be removed to expose the conductive vias 212 for electricalconnection. The removal process may comprise, for example, CMP. Removalof the materials may take place at a slower rate than a material removalperformed earlier in the process of exposing the conductive vias 212(see FIG. 4C), enabling greater control for stopping after allconductive vias 212 have been exposed, but before damaging theconductive vias 212, substrate 216, or both.

The removal process may be stopped when one or more laterally extendingportions of the barrier material 224 are exposed in some embodiments. Insuch embodiments, at least one portion of the conformal isolationmaterial 230 located between conductive vias 212 may be completelyremoved, which portion may be located, for example, over a thickestportion of the substrate 216. Because the thickness T_(BM) (see FIG. 3C)of the barrier material 224 is less than a difference between theelevation of the thickest portion of the substrate 216 and theprotruding height H₂ (see FIG. 4C) of the shortest conductive via 212B,stopping removal after encountering a laterally extending portion of thebarrier material 224 may ensure that all conductive vias 212 are exposedfor electrical connection. In other embodiments, the removal process maybe stopped when one or more laterally extending portions of theconformal isolation material 230 are exposed. In such embodiments, atleast one remaining portion of the self-planarizing isolation material226 located between conductive vias 212 may be completely removed, whichportion may be located, for example, over a thickest portion of thesubstrate 216. Because the combined thickness T_(C) (see FIG. 4A) of thebarrier material 224 and the conformal isolation material 230 may beless than a difference between the elevation of the thickest portion ofthe substrate 216 and the protruding height H₂ (see FIG. 4C) of theshortest conductive via 212B, stopping removal after encountering alaterally extending portion of the conformal isolation material 230 mayguarantee that all conductive vias 212 are exposed for electricalconnection.

Exposure of the conformal isolation material 230 or the barrier material224 may provide a detectable difference (e.g., a signal or anindication) for when to stop the material removal process. For example,exposure of the conformal isolation material 230, the barrier material224, or both may exhibit any of the properties described previously withregard to the barrier material 224 alone in connection with FIG. 3F thatare significantly different from the properties of immediately overlyingmaterials (e.g., the conformal isolation material 230 or theself-planarizing isolation material 226). When measurements of thoseproperties fall below or exceed a preselected threshold, the materialremoval process may stop.

As described previously in connection with FIG. 3G, the material removalprocess may be optimized to remove more or less of the materialsoverlying the material used to provide a stopping signal, whether thespecific signaling material be the barrier material 224 or the conformalisolation material 230.

Accordingly, disclosed herein is a method of exposing conductive vias ofa semiconductor device comprising conformally forming a barrier materialover conductive vias extending from a backside surface of a substrate. Aconformal isolation material may be formed over the barrier material. Aself-planarizing isolation material may be formed over the conformalisolation material. An exposed surface of the self-planarizing isolationmaterial may be substantially planar. A portion of the self-planarizingisolation material, a portion of the conformal isolation material, aportion of the barrier material, and a portion of protruding material ofthe conductive vias may be removed to expose the conductive vias.Removal of the self-planarizing isolation material, the barriermaterial, and the conductive vias may be stopped after exposing alaterally extending portion of the conformal isolation material.

With reference to FIGS. 5A through 5D, cross-sectional views of asemiconductor device 210″ in yet another process for exposing conductivevias 212 of the semiconductor device 210″ are shown. After the barriermaterial 224 has been conformally formed over the conductive vias 212and the backside surface 218 of the substrate 216 (see FIG. 3C), a firstself-planarizing isolation material 226A may be formed over the barriermaterial 224, as shown in FIG. 5A. The first self-planarizing isolationmaterial 226A may be formed, for example, at a thickness greater thanthe height H₂ of the shortest conductive via 212B but less than theheight H₁ of the tallest conductive via 212A. The first self-planarizingisolation material 226A may not conform to the topography of the barriermaterial 224, rendering the resulting topography significantly differentfrom the topography of the barrier material 224 prior to deposition ofthe first self-planarizing isolation material 226A. For example, thefirst self-planarizing isolation material 226A may be flowable toself-planarize. More specifically, a precursor material of the firstself-planarizing isolation material 226A may exhibit, for example, asufficiently low viscosity to flow around the protruding portions of theconductive vias 212, including any associated spacer material 213, andover the backside surface 218 of the substrate 216 under the influenceof gravity and in some cases, centrifugal force, upon deposition. Thefirst self-planarizing isolation material 226A may be formed over thebarrier material 224 using a deposition process conventionally used forflowable materials, such as, for example, spin coating or nozzledispensing. After depositing, the precursor material of the firstself-planarizing isolation material 226A may be cured to harden thefirst self-planarizing isolation material 226A. For example, the firstself-planarizing isolation material 226A may comprise a self-planarizingprecursor material, such as poly(methyl methacrylate), poly(2,2,2tri-fluoro-ethyl methacrylate), poly(dimethyl-siloxane), or AL-X2000 (acommercially available fluoropolymer), which may be spin-coated over thebarrier material 224. The self-planarizing precursor material of thefirst self-planarizing isolation material 226A may then be cured usingH₂O₂ at about 80° C. to about 120° C. to form silicon oxide (e.g.,SiO₂). In some embodiments, ultraviolet radiation may be applied tospeed up the curing process.

Referring to FIG. 5B, a second self-planarizing isolation material 226Bmay be formed over the first self-planarizing isolation material 226A.The second self-planarizing isolation material 226B may not conform tothe topography of the first self-planarizing isolation material 226A andany protruding conductive vias 212, which may render the resultingtopography significantly different from the topography of the firstself-planarizing isolation material 226A and any protruding conductivevias 212 prior to deposition of the second self-planarizing isolationmaterial 226B. For example, the second self-planarizing isolationmaterial 226B may be a non-conformal, flowable material. Morespecifically, the second self-planarizing isolation material 226B mayexhibit, for example, a sufficiently low viscosity to flow around theprotruding portions of the conductive vias 212 and over the firstself-planarizing isolation material 226A under the influence of gravityand in some cases, centrifugal force. The second self-planarizingisolation material 226B may be formed over the first self-planarizingisolation material 226A using a deposition process conventionally usedfor flowable materials, such as, for example, spin-coating or nozzledispensing, which may be followed by a curing process to harden thesecond self-planarizing isolation material 226B. The secondself-planarizing isolation material 226B may comprise, for example, anyknown resist material or spin-on dielectric. The material of the secondself-planarizing isolation material 226B may be different from thematerial of the first self-planarizing isolation material 226A.

A combined thickness T_(CSPIM) of the first and second self-planarizingisolation materials 226A and 226B may be sufficiently great tostructurally support the protruding portions of the conductive vias 212,including any associated spacer material 213, during subsequent exposureprocesses. For example, the combined thickness T_(CSPIM) of the firstand second self-planarizing isolation materials 226A and 226B may begreater than the protruding height H₁ of the tallest protruding portionof a conductive via 212A. More specifically, the combined thicknessT_(CSPIM) of the first and second self-planarizing isolation materials226A and 226B may be, for example, greater than about 2 μm, greater thanabout 5 μm, or even greater than about 10 μm.

The respective materials for first self-planarizing isolation material226A and second self-planarizing isolation material 226B may be selectedsuch that a removal rate of the second self-planarizing isolationmaterial 226B may be significantly different from (e.g., faster than) aremoval rate of the first self-planarizing isolation material 226A dueto differences in material properties (e.g., abrasion-resistance,hydrophobia, hydrophilia) or chemical response. For example, the secondself-planarizing isolation material 226B may be softer and less abrasionresistant than the first self-planarizing isolation material 226A. Inaddition, the second self-planarizing isolation material 226B may beremovable using a selective material removal process (e.g., a selectivedry etch), which may not remove the first self-planarizing isolationmaterial 226A, in some embodiments.

In some embodiments, some or all of the second self-planarizingisolation material 226B, and optionally a portion of the firstself-planarizing isolation material 226A, may be removed, as shown inFIG. 5C, to reduce the combined thickness T_(CSPIM)′ of the first andsecond self-planarizing isolation materials 226A and 226B. The partialremoval may be done using relatively fast material removal methods(e.g., selective dry etch or aggressive CMP) to reduce processing time.More specifically, a portion of the second self-planarizing isolationmaterial 226B may be removed at a rate faster than a rate of removal fora conformal isolation material 116 (see FIG. 1E) comprising siliconoxide using CMP. For example, a selective material removal process(e.g., a selective dry etch) may be used to remove some of the secondself-planarizing isolation material 226B, leaving the firstself-planarizing isolation material 226A, the barrier material 224, andthe conductive vias 212, including any associated spacer material 213,intact. After selectively removing a portion of the secondself-planarizing isolation material 226B, portions of the conductivevias 212, particularly the tallest conductive vias 212, and associatedbarrier material 224 may protrude from the second self-planarizingisolation material 226B. As another example, a non-selective materialremoval process (e.g., CMP) may be used to remove some of the secondself-planarizing isolation material 226B, portions of the conductivevias 212, particularly the tallest conductive vias 212, and associatedportions of the barrier material 224. Partial removal may leavesufficient portions of the first and second self-planarizing isolationmaterials 226A and 226B, or just the first self-planarizing isolationmaterial 226A, between the conductive vias 212 to provide structuralsupport during subsequent material removal processes, reducing (e.g.,preventing) the occurrence of toppling.

As shown in FIG. 5D, all of the second self-planarizing isolationmaterial 226B (see FIG. 5C), a portion of the first self-planarizingisolation material 226A, a portion of the barrier material 224, and aportion of the protruding sections of the conductive vias 212, includingany associated spacer material 213, may be removed to expose theconductive vias 212 for electrical connection. The removal process maycomprise, for example, CMP. Removal of the materials may take place at aslower rate than a material removal performed earlier in the process ofexposing the conductive vias 212 (see FIG. 5C), enabling greater controlfor stopping after all conductive vias have been exposed, but beforedamaging the conductive vias 212, substrate 216, or both.

The removal process may be stopped when one or more laterally extendingportions of the barrier material 224 are exposed. In other words, atleast one portion of the first self-planarizing isolation material 226Alocated between conductive vias 212 may be completely removed, whichportion may be located, for example, over a thickest portion of thesubstrate 216. Because the thickness T_(BM) (see FIG. 3C) of the barriermaterial 224 is less than a difference between the elevation of thethickest portion of the substrate 216 and the protruding height H₂ (seeFIG. 3E) of the shortest conductive via 212B, stopping removal afterencountering a laterally extending portion of the barrier material 224may guarantee that all conductive vias 212 are exposed for electricalconnection.

The barrier material 224 may provide a detectable difference (e.g., asignal or an indication) for when to stop the material removal process.For example, exposure of the barrier material 224 may exhibit any of theproperties described previously in connection with FIG. 3F that aresignificantly different from the properties of immediately overlyingmaterials (e.g., the first self-planarizing isolation material 226A).When measurements of those properties fall below or exceed a preselectedthreshold, the material removal process may cease.

As described previously in connection with FIG. 3G, the material removalprocess may be optimized to remove more or less of the materialsoverlying the barrier material 224 used to provide a stopping signal.

Referring to FIG. 6, an electronic system 232 comprising a semiconductordevice 210, 210′, or 210″, such as, for example, any of those shown inFIGS. 3F, 3G, 4D, and 5D, is shown. More specifically, the electronicsystem 232 may comprise a first semiconductor device 210, 210′, or 210″operatively connected to a second semiconductor device 234. For example,the conductive vias 212 of the first semiconductor device 210, 210′, or210″ may be electrically connected to bond pads 236 of the secondsemiconductor device 234 using conductive bumps 238. In someembodiments, an underfill material 240 may be flowed into a spacedefined between the first semiconductor device 210, 210′, or 210″ andthe second semiconductor device 234 and around the conductive bumps 238.The second semiconductor device 234 may comprise any of thosesemiconductor devices described previously in connection with FIG. 3A.For example, the second semiconductor device 234 may be the same orsubstantially the same as the first semiconductor device 210, 210′, or210″.

Accordingly, disclosed herein are electronic systems comprising a firstsemiconductor device. The first semiconductor device may compriseconductive vias in a substrate, the conductive vias comprising exposedsurfaces at a backside surface of the substrate. A barrier materialcomprising silicon nitride, silicon oxide, silicon carbide, or anycombination of these may surround the conductive vias. Aself-planarizing isolation material may be located over at least aportion of the barrier material and between the conductive vias. Atleast one laterally extending portion of the barrier material may beexposed adjacent an associated conductive via. A second semiconductordevice may be operatively connected to the first semiconductor device.

While certain illustrative embodiments have been described in connectionwith the figures, those of ordinary skill in the art will recognize andappreciate that embodiments encompassed by the disclosure are notlimited to those embodiments explicitly shown and described herein.Rather, many additions, deletions, and modifications to the embodimentsdescribed herein may be made without departing from the scope ofembodiments encompassed by the disclosure, such as those hereinafterclaimed, including legal equivalents. In addition, features from onedisclosed embodiment may be combined with features of another disclosedembodiment while still being within the scope of the disclosure, ascontemplated by the inventors.

What is claimed is:
 1. A method of exposing conductive vias of asemiconductor device, comprising: positioning a barrier material overconductive vias extending from a backside surface of a substrate to atleast substantially conform to the conductive vias; positioning aself-planarizing isolation material on a side of the barrier materialopposing the substrate, wherein an exposed surface of theself-planarizing isolation material is at least substantially planar;removing a portion of the self-planarizing isolation material, a portionof the barrier material, and a portion of at least some of theconductive vias to expose each of the conductive vias; and stoppingremoval after exposing at least one laterally extending portion of thebarrier material proximate the substrate.
 2. The method of claim 1,wherein positioning the barrier material over the conductive viasextending from the backside surface of the substrate to at leastsubstantially conform to the conductive vias comprises positioning abarrier material comprising silicon nitride, silicon oxide, siliconcarbide, or any combination of these over the conductive vias extendingfrom the backside surface of the substrate to at least substantiallyconform to the conductive vias.
 3. The method of claim 1, whereinpositioning the barrier material over the conductive vias to at leastsubstantially conform to the conductive vias comprises depositing thebarrier material to a thickness less than a protruding height of ashortest protruding portion of any of the conductive vias.
 4. The methodof claim 3, wherein depositing the barrier material to the thicknessless than the protruding height of the shortest protruding portion ofany of the conductive vias comprises depositing the barrier material toa thickness of about 15,000 Å or less.
 5. The method of claim 4, whereindepositing the barrier material to the thickness of 15,000 Å or lesscomprises depositing the barrier material to a thickness of betweenabout 800 Å and about 2,500 Å.
 6. The method of claim 1, whereinremoving the portion of the self-planarizing isolation material, theportion of the barrier material, and the portion of the at least some ofthe conductive vias to expose each of the conductive vias comprisesselectively removing a first portion of the self-planarizing isolationmaterial at a first rate and subsequently removing a second portion ofthe self-planarizing isolation material, the portion of the barriermaterial, and the portion of the at least some of the conductive vias ata second, slower rate.
 7. The method of claim 1, further comprisingstopping the removal in response to detecting a change in rate ofremoval of at least one of the self-planarizing isolation material, thebarrier material, and the at least some of the conductive vias, a changein amount of ammonia gas present, or a change in light reflectivity ofthe semiconductor device.
 8. The method of claim 1, wherein stopping theremoval comprises stopping the removal after exposing an entire uppersurface of the barrier material extending laterally over the backsidesurface of the substrate.
 9. The method of claim 1, further comprisingremoving a portion of the substrate at the backside surface to exposeportions of the conductive vias above the backside surface beforeconformally positioning the barrier material over the conductive vias.10. The method of claim 1, wherein positioning the self-planarizingisolation material on the side of the barrier material opposing thesubstrate comprises positioning a first self-planarizing isolationmaterial on the side of the barrier material opposing the substrate andpositioning a second, different self-planarizing isolation material on aside of the first self-planarizing isolation material opposing thebarrier material.
 11. The method of claim 10, wherein positioning thefirst self-planarizing isolation material on the side of the barriermaterial opposing the substrate and positioning the second, differentself-planarizing isolation material on the side of the firstself-planarizing isolation material opposing the barrier materialcomprises positioning a first self-planarizing isolation materialexhibiting a first removal rate on the side of the barrier materialopposing the substrate and a second self-planarizing isolation materialexhibiting a second, faster removal rate on the side of the firstself-planarizing isolation material opposing the barrier material. 12.The method of claim 1, further comprising positioning an at leastsubstantially conformal isolation material comprising an oxide or anitride on the side of the barrier material opposing the substratebefore positioning the self-planarizing isolation material on the sideof the barrier material opposing the substrate, the at leastsubstantially conformal isolation material being interposed between theself-planarizing isolation material and the barrier material.
 13. Asemiconductor device, comprising: conductive vias extending through athickness of a substrate, each of the conductive vias comprising anexposed surface proximate a backside surface of the substrate; a barriermaterial laterally adjacent to portions of the conductive vias extendingfrom the backside surface of the substrate and extending over thebackside surface of the substrate; and a self-planarizing isolationmaterial located on a side of at least a portion of the barrier materialopposing the substrate, wherein at least one laterally extending portionof the barrier material proximate the substrate is exposed adjacent anassociated conductive via of the conductive vias.
 14. The semiconductordevice of claim 13, wherein exposed surfaces of the conductive vias, thebarrier material, and the self-planarizing isolation material are atleast substantially coplanar.
 15. The semiconductor device of claim 13,wherein the barrier material comprises silicon nitride, silicon oxide,silicon carbide, or any combination of these.
 16. The semiconductordevice of claim 13, wherein a thickness of the barrier material is lessthan a difference in elevation between the backside surface of thesubstrate at a thickest portion of the substrate and a protrudingportion of a conductive via.
 17. The semiconductor device of claim 16,wherein the thickness of the barrier material is about 15,000 Å or less.18. The semiconductor device of claim 17, wherein the thickness of thebarrier material is between about 800 Å and about 2,500 Å.
 19. Thesemiconductor device of claim 13, further comprising an at leastsubstantially conformal isolation material comprising silicon oxideinterposed between the barrier material and the self-planarizingisolation material.
 20. The semiconductor device of claim 13, whereinthe self-planarizing isolation material exhibits a first removal rateand the barrier material exhibits a second, slower removal rate.